Ancestors

Toot

Written by error on 2024-12-14 at 11:01

For the bus enthusiasts 🚌

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Descendants

Written by error on 2024-12-14 at 18:46

Made with LaTeX, TikZ and @ada's https://gitlab.com/ada.loveless/tex-networks

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Written by kaia on 2024-12-14 at 11:11

@Error (not technical person) why does the PCI-e slots show such a great distance to GPU when GPU is connected via PCI-e?

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Written by grillchen on 2024-12-14 at 11:18

@kaia @Error the whole south/north bridge thingie is mostly outdated. and also only important for amd/intel products.

it was true before pci was even a thing. i think it is mostly for integrated gpus or if the gpu is connected via the old agp thingie rather than pci-e

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Written by grillchen on 2024-12-14 at 11:27

@kaia @Error here is a graphic about the wishbone bus. a very flexbile, minimalistic open source/hardware bus. u can add more devices.

it uses the master slave setup. masters can read/write from slaves. no other direct communication allowed (very few exceptions).

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Written by twinspin :neofox_cofe: on 2024-12-14 at 11:29

@grillchen @kaia @Error >cpu (optional)

:naruhodo:

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Written by grillchen on 2024-12-14 at 12:28

@twinspin6 @kaia @Error it is^^

this makes it very nice for specific hardware devices like: fpgas, controller devices, device cards like wifi card or something.

a cpu is not stricly necessary

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Written by Howard Chu @ Symas on 2024-12-14 at 21:48

@grillchen @kaia @Error @twinspin6 if there is no CPU, what is the master?

A multimaster bus like VMEbus or even Firewire makes more sense when you want to connect a bunch of independent devices

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Written by grillchen on 2024-12-14 at 23:30

@hyc @kaia @Error @twinspin6 i know SD cards can be master. For example to program an fpga over it.

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Written by Wolf480pl on 2024-12-14 at 11:47

@kaia @Error (technical person)

Why is there a DDR5 in a platform old enough to still have a northbridge?

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Written by Kelly MacNeill on 2024-12-14 at 16:35

@wolf480pl @kaia @Error my thoughts as well

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Written by gettie (:neogettie_floof: arc) :OwOid: :verified_neko: :neocat_flag_ace: :neocat_flag_nb: on 2024-12-14 at 11:13

@Error as far as i know, the northbridge and the southbridge station have been merged to the chipset station, but it's a pretty good explanation, i love it

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Written by Zimmie on 2024-12-14 at 13:38

@getimiskon @Error The Northbridge handled high-speed I/O like talking to the RAM. That has all been merged into the CPU directly.

The rest of the chipset is basically just the Southbridge: low-speed stuff like USB, SATA, and slow PCIe lanes (a lot of systems have PCIe 3 or 4 from the processor directly, but a bunch of peripherals only need PCIe 2 from the Southbridge). Some processors are also taking this over. For example, Intel’s Atom C2000 and C3000 lines provide everything from the processor.

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Written by The Lack Thereof on 2024-12-14 at 17:41

@bob_zim @getimiskon

But they still exist from an architectural standpoint, they've just been physically relocated

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Written by Zimmie on 2024-12-14 at 17:54

@lackthereof @getimiskon It’s all one die for the C2000 and C3000 lines, it just talks to some cores internally using PCIe signaling instead of FSB/HT/QPI/UPI/&c. There’s no option with those parts to use a separate PCH or anything. Thus, they’re integrated into the CPU.

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Written by Cal Alaera :SpoonsOutlined: on 2024-12-14 at 11:22

@Error What did you use to draw this? It looks awesome!

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Written by error on 2024-12-14 at 12:08

@Cal Thank you; It's LaTeX and TikZ

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Written by Andy on 2024-12-14 at 11:49

@Error FSB? What century is this?

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Written by Tom Merlin on 2024-12-14 at 12:09

@G33KatWork @Error Yeah, that is still called KGB! scnr

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Written by Veronica Olsen 🏳️‍🌈🇳🇴🌻 on 2024-12-14 at 12:09

@Error Hah, rarely have I seen a better example of the Mastodon commenter tendency to miss the point entirely and go off into well actuallys.

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Written by Martijn 🇪🇺🇳🇱 on 2024-12-14 at 13:05

@veronica @Error 😂

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Written by SuperIlu on 2024-12-14 at 12:12

@Error Wait, ISA and PCI services are discontinued?

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Written by Harald Hannelius :verified: on 2024-12-14 at 17:17

@dec_hl @Error still dreaming on how to manage my IRQ, DMA and I/O.

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Written by SuperIlu on 2024-12-14 at 17:18

@harald @Error you will be fine as long as you still have all manuals which tell you which jumper is which in the cards 😊

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Written by Rob Landley on 2024-12-14 at 12:29

@Error We need a mornington crescent adapter

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Written by Quinn Norton on 2024-12-14 at 12:56

@Error goddamnit.

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Written by Chris 🦑 on 2024-12-14 at 12:59

@Error liebs!

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Written by Ronflaix on 2024-12-14 at 13:21

@Error yeee rambus goes vroom vroom

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Written by ↸ ⏚ on 2024-12-14 at 13:32

@Error ping @AndreasSebayang

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Written by Andreas Sebayang on 2024-12-15 at 09:15

@subtruth @Error Sehr Cool. :)

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Written by David Adam on 2024-12-14 at 13:32

@Error this would do major numbers on NUMTOT

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Written by jgeorge on 2024-12-14 at 13:42

@Error I LOVE this.

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Written by Geert Uytterhoeven on 2024-12-14 at 14:25

@Error PCIe is not a bus, but point-to-point

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Written by penguin42 on 2024-12-14 at 15:12

@geert @Error And the tube map isn't a geographical map of London.

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Written by SouthFresh on 2024-12-14 at 16:18

@Error So uh, where's the terminal?

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Written by penguin42 on 2024-12-14 at 17:55

@SouthFresh @Error Hopefully on the end of the SCSI bus.

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Written by Joseph Horgan on 2024-12-14 at 21:05

@Error I'm not a developer of software or hardware, but it seems to me that M.2 drives with a dynamic swap partition could obviate the need for RAM. Want more RAM? Edit your partitions.

Am I wrong?

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Written by Howard Chu @ Symas on 2024-12-14 at 21:52

@josephpmh @Error yes, you are wrong. NVMe drives are still orders of magnitude slower than RAM.

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Written by Rue Mohr on 2024-12-14 at 21:23

@Error

:[ you missed the tap for ISA

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Written by Sylvhem on 2024-12-15 at 01:05

@Error That may be one of the clearer diagrams I have seen explaining PC buses.

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Written by :bun: Stellar 🇫🇷 (:blahaj: era) on 2024-12-15 at 02:18

@Error@chaos.social this pic goes hard

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Written by John Carlsen 🇺🇸🇳🇱🇪🇺 on 2024-12-15 at 02:18

@Error

I recall that on the K8 the DDR connected directly to the CPU, which also had 3 HT interfaces that could be used as a FSB to the northbridge or connect to other CPUs.

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Written by Tim Clevenger :donor: on 2024-12-15 at 02:28

@Error Many years ago I printed on a wide format printer and framed the Milky Way Transit Authority system map. It's still on the wall in my office.

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Written by Apicultor 🐝 on 2024-12-15 at 09:51

@Error s/bus/transport/

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Written by vermaden on 2024-12-15 at 09:57

@Error

Now NUMA please :)

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Written by Iska on 2024-12-23 at 00:12

@Error@chaos.social FSB and quad-channel DDR5 in the same picture, this is too cursed

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