Out of the oven and looking good. Two shorts on the clock generator QFN (southwest of FPGA in middle). That was definitely from too thick paste from the stencil issue near the middle of the board.
This is going to take me a while to bring up. I've not yet started porting the RP2040 firmware from the power test board to the STM32L422 on this. Should be straightforward given it's Rust embedded HAL for the I2Cs. The LMK05381B clock will be a first use for me and will require some programming.
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Maybe some stepped blocks like @azonenberg uses around the outside and some pucks of the same height to distribute in areas with no components on the back side.
Will probably try that in ESD-PETG FDM 3D print. Tops and bottoms of parts should be nice even if sides have the usual FDM blobs.
The dowel pins to align the stencil are great.
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Getting back on stuffing the buffer board after a long break.
Paste print looks very good, but I got lucky that nothing fine pitch is in the middle. The board was flexing down there leaving paste on top of the stencil.
Biggest board I've ever pasted, also being 1.2 mm thick made things harder.
I'm going to have to get some support under the middle of the board before stuffing the RFSoC which is even bigger and also 1.2 mm.
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2022 date code on these. From Digikey af few months ago. That's definitely not the right tape for the part. Very deep pockets, too big and has a bump to support the body of a leaded part.
Good thing I'm hand placing.
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Overclocking margin measurement on Ultrascale+. This design failed timing for 500 MHz with 35 ps of negative slack for a -2 part which was my intent.
Here it's loaded into an XCAU10P-1 from Digikey, running at 32 C and 0.845 V.
Pretty impressive what it managed before giving up. Doing 2^20 rounds of AES-CBC for a good workout with massive error propagation.
Doing this to screen a bunch of unknown speed grade gray market KU5Ps.
Also capturing IDELAYE3 tap delay, 3.6979 ps in this case.
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Any clock signal that reaches the ADC input will alias to 0 Hz so will just result in a small and constant DC offset which is no problem. The bigger issue is the ADC input signal getting on the clock. Each clock pair is used for two ADCs and clean clocks are crucial.
I may end up making a board that gets BGA balls and solders on the back. That way, effectively I have a 20 layer board in this area with blind vias layers 1-10 and 11-20.
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I had the clock baluns on the back of the board, coax jumpers over the ADC inputs, decided that would be difficult to impossible to fabricate and install a shield for.
The below is the best I can do in a through via board, I don't like it. The eval used blind vias for the ADC input so there was an unbroken plane between the clock and input. Not going to spend $2k+ to make that happen.
May not be the worst thing as there is minimal differential mode coupling due to symmetry.
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A little more teardown, not much left aside from the die and a tiny bit of substrate.
Die is now cracked. Not sure if I did that or if it came that way.
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I forgot to mention that this part had loose decoupling caps rattling around under the heat spreader. They either dropped or tapped it while hot. The part is consistent with Murata LLL1U4D80E435ME22D which is a 4.3 uF 0204.
I'm going to to a little more milling into the substrate and then send the die off to @azonenberg for some imaging.
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This is a Xilinx XCKU5P FPGA in the FFVB676 package. It's the only part of 10 that I got from a few Aliexpress sellers for cheap that didn't work. This one appears to have been overheated in a reballing attempt. The substrate is delaminated as can be seen in the cross section.
14 layer HDI PCB. It's built as a 2 layer 1 mm thick board with 6 plies of resin clad copper (no fiberglass) laminated on. This probably went in a lamination press 6 times with laser vias, plating and etching in between.
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The DRAM section of the RFSoC board is going to work in 10 layers. This does need a cleanup pass and length matching on the PS hard memory controller side.
12 rows deep with just 4 routing layers. Really more like 3.5 layers as one has a power planelet on it. Two traces between vias makes quite a difference. Pin placement wasn't totally free as this is using native mode IO on US+ with byte lanes.
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Does anyone have a favorite LED for 1.8 V IO? Don't care color, just looking for a low brightness indicator on a PCB. Brightness can vary somewhat unit to unit.
That does seem questionable given how close 1.8 V is to forward voltage of even red LEDs. I could use a transistor and run the LEDs from the ~5V input supply but it would be nice to drive directly from the IO.
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Do any of you ever use a JTAG chain consisting of multiple chips on a board? I'm working on a JTAG tool for Xilinx FPGAs and SOCs, trying to decide to support this or not.
Zynq has a scan chain of multiple TAPs as do multiple SLR FPGAs but those few cases are a lot simpler than some other vendor part plus one of these.
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The coverlay is thick enough to align the BGA by feel.
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Attempt at a solderless test board for Xilinx Ultrascale+ parts in the FFVB676 package (AU10P-KU5P) and FFVE1156 (various Zynq RFSoC). I forgot a part and Digikey seems to take a few days to ship now but hopefully this will work.
Initial tests are promising with all JTAG pins having a protection diode to ground through the pressure interface.
This is 25 um polyimide with 12 um copper so very flexible. I'm backing it with 0.5 mm silicone rubber, a piece of thick metal. The stack gets clamped.
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I likely won't give it any flash, will emulate flash with a block RAM to provide it a bootloader which will then fetch the program from the FPGA configuration flash.
For development purposes, I'll upload code via SWD.
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I'm interested in using RP2350A on my DDR5 test board but it seems I can't buy just the chips. Pi Pico 2's are available and I guess I could desolder. Looks like the updated QSPI interface should be able to support memory mapped register access in the FPGA. Given the low cost and pin count, I may make this something I throw in on most FPGA boards I build if it works out.
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I want to make a test fixture for Xilinx Ultrascale+ parts in the FFVB676 package so I can verify parts sourced from gray market vendors are good. Only need to contact about 20 pins so I'm thinking of pogo pins, an aligner fixture. Part is 1 mm pitch, no two adjacent pins are required but that would be nice to have for a differential clock input. On package decoupling, minimal load so some inductance is tolerable. Any better ideas that could be implemented economically? A proper socket is $$$$.
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There was more edge bond on the corners than the Xilinx docs call for. It was only supposed to go slightly under the part, not touch the balls but it went past the first row of balls in places.
I knew it was a gamble.
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The delamination is on the top of the part in some layers using resin clad copper and no fiberglass.
I did bake at 125 C for 4 hours prior and it was preheated to 150 C before any hot air.
I probably should have practiced more with junk graphics cards for experience with giant packages but the edge bonding still would have been an issue.
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