I had the clock baluns on the back of the board, coax jumpers over the ADC inputs, decided that would be difficult to impossible to fabricate and install a shield for.
The below is the best I can do in a through via board, I don't like it. The eval used blind vias for the ADC input so there was an unbroken plane between the clock and input. Not going to spend $2k+ to make that happen.
May not be the worst thing as there is minimal differential mode coupling due to symmetry.
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Any clock signal that reaches the ADC input will alias to 0 Hz so will just result in a small and constant DC offset which is no problem. The bigger issue is the ADC input signal getting on the clock. Each clock pair is used for two ADCs and clean clocks are crucial.
I may end up making a board that gets BGA balls and solders on the back. That way, effectively I have a 20 layer board in this area with blind vias layers 1-10 and 11-20.
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It's not perfect but it's a big improvement. The 4 clock pairs are routed as 90 um trace / 110 um trace to fit between vias which is closer to 90 ohms than the ideal 100 but will be fine.
Edit: the ADC input traces are on layer 8 with layers 7 and 9 cleared in their area. Ground planes are on 6 and 10 for those. This gives wider traces and lower loss.
The clocks are on layers 3, 5, 7, 9 with grounds on 2, 4, 6, 8, 10 in that area.
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The DACs are done a little different. This is a 10 GHz clock, Xilinx states the skew must be less than 4 ps so I wished to avoid any asymmetrical routing.
The baluns are from TTM (formerly Anaren), should give less than 2 ps skew given their phase error spec. Surprisingly cheap for an X band part at < $2.
The splitter in the middle is a Wilkinson. Those lines are 70.7 ohms nominally. Similar width to 50 ohms but the closest ground layer is cleared.
The SMP doesn't really have that tab.
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I was a bit surprised to see the TTM brand on those baluns. TTM is a big US PCB manufacturer. They have built some of my designs in the past. Quite capable but expensive.
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@dlharmon How big would a 180 degree rat race hybrid for 10 GHz be? That'd be my first thought.
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@dlharmon Also at Multech IIRC it's only a $100 or 150 cost adder to do one level of blind or buried vias.
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@azonenberg It would need two levels of blind vias which should be a much bigger cost adder.
This monstrosity is the eval board stack.
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@dlharmon My first design with them was in 2013 or so and was a touch under $1K iirc. 6 layers but with stacked blind/buried microvias from 1-2 and 2-3.
I've been shocked at how cheap some high end specs are with them. I used to think ViP was something exotic now I use it on almost every design.
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@azonenberg @dlharmon tbf ViP is free on JLC's 6L stackup now anyway. it's mostly microvias where you pay the big bucks. (and JLC doesn't support blind/buried at all)
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@azonenberg If I was starting over, I'd probably at least get a quote on something like the upper 12 layers of that Xilinx stack.
It's been a lot of work but I'm actually feeling pretty good about signal and power integrity on this 10 layer JLC 1.15 mm thick VIPPO stack.
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@dlharmon Yeah you can definitely get by with less layers than a lot of eval boards.
The 6L board I mentioned was for a chip where the TI EVM was like 8 or 10 layers and used several more levels of blind/buried vias than my design did.
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@azonenberg A lot of it here is the DRAM layout. They used thicker prepregs and cores, only one trace between BGA balls. It's 12 rows deep in the DRAM area. I went with the 1.15 mm stack that gives about a 95 um 50 ohm line allowing two traces between vias, much thinner DRAM traces. UG583 even allows for how I did it.
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@dlharmon Yeah I'm a big fan of very thin prepreg for high density layout as long as loss isn't a major issue.
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@azonenberg I do have an idea in my head that will need somewhat exotic laminate (similar to Isola Astra MT77 or Tachyon 100G) and HDI, will have to talk to them when I'm ready to start it. Probably next winter. The hard part is a mmwave filter bank that I'd want to implement as stripline on an inner layer with blind vias to to connect to the switches on the surface. Probably $10k for a minimum order of the stack I have in mind at a US boardhouse like TTM. I'm hoping for under $2000.
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@dlharmon Multech doesn't stock those off the top of my head, but they can definitely get them on request.
They'll probably offer better prices for Asian laminates, though. Would something like this be a good option?
https://www.tuc.com.tw/en-us/products-detail/id/51
https://www.iteqcorp.com/product/product-introduction/high-tg-super-ultra-low-loss/#it-998gse2tc
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@dlharmon I've had very good experiences with TUC laminates, I use TU872SLK on most of my high speed designs these days.
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@azonenberg I'd assumed I'd be switched to something like the IT-988 which is essentially an Astra clone and that would definitely be the first order of business in discussion with them.
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@dlharmon Yeah I remember asking for Megtron6 on a design a while back and getting sticker shock, then swapping in TU872SLK and being very happy with the performance and price.
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@azonenberg A rat race would be quite reasonable and I considered that. My concern was the skew spec and fiber weave effect in how far I would have to route it to have room for that. Also a bit of Er tolerance given it's S1000-2M.
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