Toot

Written by Wanda on 2025-01-12 at 14:34

@wolf480pl kinda yeah (it's how basically all blockrams work btw)

what actually happens in hardware is slightly more complicated: the clock edge latches the address in a register, and the address is combinationally decoded into a wordline (selecting a BRAM row); then after some delay, the read strobe generator actually triggers the wordline, causing the data to appear on the bitlines; the weak signal from the bitlines is then amplified and latched into the read data latch by yet another delayed strobe

all the delays involved (and the write strobe delay of course) are actually programmable in the bitstream; they just happen to be set to fixed values by the toolchain, presumably as determined to be optimal during Spartan-3E bringup

=> More informations about this toot | View the thread | More toots from mwk@donotsta.re

Mentions

=> View wolf480pl@mstdn.io profile

Tags