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Written by Wolf480pl on 2025-01-12 at 14:01

Do I remember correctly that the way Block RAM works in Spartan-3E is

you write it as

mem_out <= mem[addr]

but in reality it's the address that gets written synchronously to the read port, and the RAM takes most of the following cycle to give you an output that behaves like a wire?

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Written by Wanda on 2025-01-12 at 14:34

@wolf480pl kinda yeah (it's how basically all blockrams work btw)

what actually happens in hardware is slightly more complicated: the clock edge latches the address in a register, and the address is combinationally decoded into a wordline (selecting a BRAM row); then after some delay, the read strobe generator actually triggers the wordline, causing the data to appear on the bitlines; the weak signal from the bitlines is then amplified and latched into the read data latch by yet another delayed strobe

all the delays involved (and the write strobe delay of course) are actually programmable in the bitstream; they just happen to be set to fixed values by the toolchain, presumably as determined to be optimal during Spartan-3E bringup

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Written by Wanda on 2025-01-12 at 14:37

@wolf480pl fun fact: early Altera devices are one of the few that have a variation on the formula, btw: to avoid having to deal with carefully calibrated delays, they decided to use the falling edge of the clock for the memory operation. so the address, write data and control lines are latched in on the rising edge, things take a bit to stabilise internally, then the falling edge actually triggers the write or gives you the read data.

this makes it incredibly annoying to deal with in any kind of generic fashion.

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Written by Wolf480pl on 2025-01-12 at 14:51

@mwk awesome, thanks for the explanation.

The BRAM using programmable sub-cycle delays in an otherwise synchronous circuit sound somewhat cursed, just the right amount of cursed for an FPGA :D

Though I'm curious why Altera's use of falling clock edge somehow ended up more cursed

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Written by Wanda on 2025-01-12 at 14:55

@wolf480pl using falling edge is fine when you have a single clock domain involved (because who cares), but makes it a pain to reason about what's going on when you have two domains involved (because you're using your BRAM as a clock domain crossing FIFO)

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Written by Wolf480pl on 2025-01-12 at 14:55

@mwk oh....

"fun"

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