Ancestors

Written by Jonathan ‘theJPster’ Pallant on 2025-01-26 at 06:59

Can anyone explain to me how SVC works in EL1 on Armv8-R? It doesn’t seem to work like Armv7-R.

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Toot

Written by Jonathan ‘theJPster’ Pallant on 2025-01-26 at 07:16

Specifically, I’m ending up in my SVC handler with a stack pointer of zero, but only on a QEMU Cortex-R52 machine. The Cortex-R5 works as expected.

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Descendants

Written by Jonathan ‘theJPster’ Pallant on 2025-01-26 at 10:19

Arm Cortex-R (and I guess ‘legacy’ Arm) is so weird.

Want to return from an exception handler? Just MOV the Link Register to the Program Counter Register.

Unless it’s an Prefetch Abort, IRQ or FIQ handler, in which case subtract 4 first.

Or if it’s a Data Abort exception, where you subtract 8 first.

This is what happens when people design an ISA and a pipelined CPU at the same time.

https://developer.arm.com/documentation/den0042/a/Exceptions-and-Interrupts/Exception-priorities/The-return-instruction

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